EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 377

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
July 2005
512
256
128
64
32
64
32
4K
2K
1K
512
256
Table 2–7. M512 Block Mixed-Width Configurations (Simple Dual-Port Mode)
Table 2–8. M4K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)
Read Port
8
16
9
18
1
2
4
1
2
4
8
16
Read Port
4K
v
v
v
v
v
1 2K
v
v
v
v
v
512
TriMatrix memory supports mixed-width configurations, allowing
different read and write port widths. When using mixed-width mode, the
LSB is written to or read from first. For example, take a RAM that is set up
in mixed-width mode with write data width ×8 and read data width ×2.
If a binary 00000001 is written to write dress 0, the following is read out
of the ×2 output side:
Tables 2–7
M4K, and M-RAM blocks, respectively.
v
v
v
v
v
00
01
10
11
2 1K
Read Address
1
v
v
v
v
v
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
256
4 512
to
v
v
v
v
v
2–9
v
v
v
v
v
2
show the mixed width configurations for the M512,
8 256
01(LSB of ×8 data)
00
00
00(MSB of ×8 data)
128
v
v
v
v
×2 data
Write Port
v
v
v
v
v
4
16 128
Write Port
64
v
v
v
v
v
v
v
v
8
32 512
Stratix Device Handbook, Volume 2
32
v
v
v
v
16
9 256
64
v
9
18 128
32
v
18
2–9
36