EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 807

IC STRATIX FPGA 40K LE 956-BGA

EP1S40B956C5

Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S40B956C5

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Figure 12–16. Converting POF Programming File to Intel HEX Format
Altera Corporation
September 2004
The initial programming file (POF) can be converted to an Intel
Hexadecimal format file (*.HEXOUT) using the Quartus II CPF utility.
See
Partial Programming File Generation
The enhanced Quartus II CPF utility allows an existing application
configuration page to be replaced with new data. Partial programming
files are generated to perform such configuration data updates.
In order to generate a partial programming file, you have to input the
initial programming file (POF) and new configuration data (SOF) to the
Quartus II CPF utility. In addition, you have to specify the addressing
mode (auto or manual) that was used during initial POF creation. And if
Figure
12–16.
Remote System Configuration with Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
12–29

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