EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 436

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Stratix & Stratix GX I/O Standards
4–8
Stratix Device Handbook, Volume 2
3.3-V 2× AGP - Intel Corporation Accelerated Graphics Port
Interface Specification 2.0
The 2 AGP I/O standard is a voltage-referenced, single-ended standard
used for 3.3-V graphics applications. The 2 AGP input standard
specifies an input voltage range of – 0.5V V
standard does not require board terminations. Stratix and Stratix GX
devices support both input and output levels.
GTL - EIA/JEDEC Standard EIA/JESD8-3
The GTL I/O standard is a low-level, high-speed back plane standard
used for a wide range of applications from ASICs and processors to
interface logic devices. The GTL standard defines the DC interface
parameters for digital circuits operating from power supplies of 2.5, 3.3,
and 5.0 V. The GTL standard is an open-drain standard, and Stratix and
Stratix GX devices support a 2.5- or 3.3-V V
GTL requires a 0.8-V V
Figure
levels.
Figure 4–4. GTL Termination
GTL+
The GTL+ I/O standard is used for high-speed back plane drivers and
Pentium processor interfaces. The GTL+ standard defines the DC
interface parameters for digital circuits operating from power supplies of
2.5, 3.3, and 5.0 V. The GTL+ standard is an open-drain standard, and
Stratix and Stratix GX devices support a 2.5- or 3.3-V V
standard. GTL+ requires a 1.0-V V
1.5-V V
input and output levels.
4–4). Stratix and Stratix GX devices support both input and output
TT
(see
Output Buffer
Figure
V
4–5). Stratix and Stratix GX devices support both
TT
REF
= 1.2 V
V
and open-drain outputs with a 1.2-V V
50 Ω
REF
Z = 50 Ω
= 0.8 V
REF
V
TT
and open-drain outputs with a
= 1.2 V
50 Ω
CCIO
I
V
to meet this standard.
CCIO
Input Buffer
+ 0.5V. The 2 AGP
Altera Corporation
CCIO
to meet this
June 2006
TT
(see