EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 566

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Architecture
6–16
Stratix Device Handbook, Volume 2
The DSP block interface generates the clock signals from LAB row clocks
or the local interconnect. The clear signals are generated from the local
interconnects within each DSP block row interface or from LAB row
clocks. The four clock enable signals are generated from the 30 local
interconnects from the same LAB rows that generate the clock signals.
The clock enable is paired with the clock because the enable logic is
implemented at the interface.
within the row interface block.
Figure 6–9. DSP Block Row Interface Signal Distribution
18-Bit Data Routed
from 30 Local
Interconnects
Four Clock Enable
Signals Routed from
30 Local Interconnects
Four Clear Signals
Routed from 30 Local
Interconnects or LAB
Row Clock
Four Clock Signals
Routed from LAB
Row Clock or Local
Interconnect
data[17..0]
Row 1
Row 2
Row 7
Row 8
ena[3..0]
18
Figure 6–9
4
aclr[3..0]
4
clock[3..0]
4
shows the signal distribution
18
18
18
18
Registers
Input
18
18
Altera Corporation
18
18
A1
B1
A4
B4
Multiplier
Multiplier
18 × 18
18 × 18
July 2005