EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 345

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
July 2005
Phase Shifting
Stratix and Stratix GX device fast PLLs have advanced clock shift ability
to provide programmable phase shift. These parameters are set in the
Quartus II software.
The Quartus II software automatically sets the phase taps and counter
settings according to the phase shift entry. Enter a desired phase shift and
the Quartus II software automatically sets the closest setting achievable.
This type of phase shift is not reconfigurable during system operation.
You can enter a phase shift (in degrees or time units) for each PLL clock
output port or for all outputs together in one shift. You can perform phase
shifting in time units with a resolution range of 125 to 416.66 ps to create
a function of frequency input and the multiplication and division factors
(that is, it is a function of the VCO period), with the finest step being equal
to an eighth ( 0.125) of the VCO period. Each clock output counter can
choose a different phase of the VCO period from up to eight taps for
individual fine-step selection. Also, each clock output counter can use a
unique initial count setting to achieve individual coarse shift selection in
steps of one VCO period. The combination of coarse and grain shifts
allows phase shifting for the entire input clock period.
Differential SSTL
3.3-V GTL
3.3-V GTL+
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-3 Class I
SSTL-3 Class II
AGP (1× and 2×)
CTT
Table 1–12. Fast PLL Port I/O Standards (Part 2 of 2)
I/O Standard
General-Purpose PLLs in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
INCLK
v
v
v
v
v
v
v
v
v
Input
PLLENABLE
1–35