EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 655

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
July 2005
AC Timing Specifications
Stratix and Stratix GX devices support a PCS interface.
8–9
transmitter and receiver interfaces.
Figure 8–8
PCS transmitter. You can determine PCS channel-to-channel skew by
adding the data invalid window before the rising edge (T
invalid window after the rising edge (T
Figure 8–8. PCS Transmitter Timing Diagram
Note to
(1)
EP1SGX10
EP1SGX25
EP1SGX40
Stratix GX Device
Table 8–3. Stratix GX Device XSBI Core Support
and
The LVDS channels can go up to 840 Mbps for flip-chip packages and up to
624 Mbps for wire-bond packages. This number includes both high speed and
low speed channels. The high speed LVDS channels can go up to 840 Mbps. The
low speed LVDS channels can go up to 462 Mbps. The High-Speed Differential I/O
Support chapter in the Stratix Device Handbook, Volume 1, and the device pin-outs
on the web (www.altera.com) specify which channels are high and low speed.
TX_DATA[15..0]
PMA_TX_CLK
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
Table
Tables 8–4
shows the AC timing diagram for the Stratix and Stratix GX
8–3:
T cq_pre
and
(Receive/Transmit)
Number of LVDS
8–5
Channels
22/22
39/39
45/45
(1)
illustrate timing characteristics of the PCS
T cq_post
Valid
Data
Stratix Device Handbook, Volume 2
cq_post
Number of Fast
PLLs
T period
).
2
2
4
T setup
Figures 8–8
cq_pre
Number of XSBI
(Maximum)
Interfaces
T hold
) to the data
1
2
2
and
8–11