EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 518

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Differential I/O Termination
Figure 5–32. Differential I/O Pin Locations
Differential I/O
Termination
5–46
Stratix Device Handbook, Volume 2
PCML, HyperTransport)
Differential I/O Pins
(LVDS, LVPECL,
f
Stratix devices implement differential on-chip termination to reduce
reflections and maintain signal integrity. On-chip termination also
minimizes the number of external resistors required. This simplifies
board design and places the resistors closer to the package, eliminating
small stubs that can still lead to reflections.
R
Stratix devices support differential on-chip termination for the LVDS I/O
standard. External termination is required on output pins for PCML
transmitters. HyperTransport, LVPECL, and LVDS receivers require
100 ohm termination at the input pins.
differential termination for the LVDS I/O standard.
For more information on differential on-chip termination technology, see
the Selectable I/O Standards in Stratix & Stratix GX Devices chapter.
AA
W
D
G
H
J
K
L
M
N
P
R
T
U
V
Y
A
B
C
D
E
F
Differential Termination
21
20
19
18
17
16
15
14
Regular I/O Pins
Regular I/O Pins
13
12
11
10
9
8
7
6
5
4
Figure 5–33
3
2
1
Differential I/O Pins
(LVDS, LVPECL,
PCML, HyperTransport)
shows the device with
Altera Corporation
July 2005