EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 445

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Stratix & Stratix
GX I/O Banks
Altera Corporation
June 2006
HyperTransport Technology - HyperTransport Consortium
The HyperTransport technology I/O standard is a differential
high-speed, high performance I/O interface standard developed for
communications and networking chip-to-chip communications.
HyperTransport technology is used in applications such as high-
performance networking, telecommunications, embedded systems,
consumer electronics, and Internet connectivity devices. The
HyperTransport technology I/O standard is a point-to-point (one source
connected to exactly one destination) standard that provides a high-
performance interconnect between integrated circuits in a system, such as
on a motherboard.
Stratix devices support HyperTransport technology at data rates up to
800 Mbps and 32 bits in each direction. HyperTransport technology uses
an enhanced differential signaling technology to improve performance.
HyperTransport technology supports data widths of 2, 4, 8, 16, or 32 bits
in each direction. HyperTransport technology in Stratix and Stratix GX
devices operates at multiple clock speeds up to 400 MHz.
UTOPIA Level 4 – ATM Forum Technical Committee Standard AF-
PHY-0144.001
The UTOPIA Level 4 frame-based interface standard allows device
manufacturers and network developers to develop components that can
operate at data rates up to 10 Gbps. This standard increases interface
speeds using LVDS I/O and advanced silicon technologies for fast data
transfers.
UTOPIA Level 4 provides new control techniques and a 32-, 16-, or 8-bit
LVDS bus, a symmetric transmit/receive bus structure for easier
application design and testability, nominal data rates of 10 Gbps, in-band
control of cell delimiters and flow control to minimize pin count, source-
synchronous clocking, and supports variable length packet systems.
UTOPIA Level 4 handles sustained data rates for OC-192 and supports
ATM cells. UTOPIA Level 4 also supports interconnections across
motherboards, daughtercards, and backplane interfaces.
Stratix devices have eight I/O banks in addition to the four enhanced PLL
external clock output banks, as shown in
banks 3, 4, 7, and 8 support all single-ended I/O standards. I/O banks 1,
2, 5, and 6 support differential HSTL (on input clocks), LVDS, LVPECL,
PCML, and HyperTransport technology, as well as all single-ended I/O
standards except HSTL Class II, GTL, SSTL-18 Class II, PCI/PCI-X 1.0,
and 1 /2 AGP. The four enhanced PLL external clock output banks
(I/O banks 9, 10, 11, and 12) support clock outputs all single-ended I/O
Selectable I/O Standards in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
Table 4–2
and
Figure
4–18. I/O
4–17