EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 606

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Finite Impulse Response (FIR) Filters
7–28
Stratix Device Handbook, Volume 2
time. The demultiplexer is controlled by a counter, which counts down
modulo-D starting at 0. The overall output is taken by adding the outputs
of all the filters.
The polyphase representation of the decimation filter also reduces the
computational requirement. For the example in
implementation requires 16
whereas the polyphase implementation requires only 4
computations per cycle. This saving in computational complexity is quite
significant and is often a very convincing reason to use polyphase filters.
Figure 7–16. Polyphase Filter Representation of a D=4 Decimation Filter
Decimation Using a Single Low-Pass Filter
Decimation Using a Polyphase Filter
Input
4x clock
x(n)
Input
x(n)
h(0), h(1), ... h(15)
coefficients
LPF with
Modulo 4 down
initialized at 0
counter
0
2
3
1
D = 16
h(2), h(6), h(10), h(14)
h(3), h(7), h(11), h(15)
h(0), h(4), h(8), h(12)
h(1), h(5), h(9), h(13)
with coefficients
with coefficients
with coefficients
with coefficients
Polyphase Filter
Polyphase Filter
Polyphase filter
Polyphase filter
D = 4
4 = 64 computations per cycle,
Figure
Output
y(n)
Altera Corporation
7–16, the direct
September 2004
4
1 = 16
Output
y(n)