EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 417

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 3–10. Bidirectional DDR I/O Path in Stratix & Stratix GX Devices
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Altera Corporation
June 2006
All control signals can be inverted at the IOE. No programmable delay chains are shown in this diagram.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before input to the A
The A
This select line is to choose whether the OE signal should be delayed by half-a-clock cycle.
The B
The tristate enable is active low by default. You can design it to be active high. The combinational control path for
the tristate is not shown in this diagram.
You can also have combinational output to the I/O pin; this path is not shown in the diagram.
Figure
OE
OE
register generates the delayed enable signal for the write strobes and write clock for memory interfaces.
register generates the enable signal for general-purpose DDR I/O applications.
3–10:
Logic Array
dataout_h
dataout_l
(4)
datain_h
outclock
combout
OE
inclock
datain_l
OE
register during compilation.
(2)
Latch C
Latch
Q
ENA
TCHLA
Output Register A
Output Register B
External Memory Interfaces in Stratix & Stratix GX Devices
OE Register B
I
D
OE Register A
DFF
DFF
DFF
DFF
D
D
D
D
neg_reg_out
Q
Q
Q
Q
OE
OE
O
O
(5)
(3)
Input Register A
Input Register B
Q
Q
DFF
DFF
0
1
D
D
0
1
I
I
Stratix Device Handbook, Volume 2
OR2
Note (1)
TRI
(6)
I/O Pin (7)
3–21