EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 714

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Configuration
Configuration
10–30
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
(3)
registered_input
common_rx_tx_pll
Table 10–12. New altlvds Parameters for Stratix LVDS Transmitter (Part 2 of 2)
You can specify these parameters in the MegaWizard Plug-In Manager.
You must specify a data rate in the MegaWizard Plug-In Manager instead of a W factor.
The same fast PLL can be used to clock both the receiver and transmitter only if both are running at the same
frequency.
Tables 10–11
Parameter
and 10–12:
(3)
Above the standard I/O offered by APEX II, APEX 20K, and Stratix
devices, Stratix GX devices provide up to 20 3.175 Gbps transceivers. The
transceivers provide high-speed serial links for chip-to-chip, backplane,
and line-side connectivity and support a number of the emerging
high-speed protocols. You can find more information in the Stratix GX
Family Data Sheet in the Stratix GX Family Handbook, Volume 1.
The Stratix and Stratix GX devices supports all current configuration
schemes, including the use of enhanced configuration devices, passive
serial (PS), passive parallel asynchronous (PPA), fast passive parallel
(FPP), and JTAG. Stratix and Stratix GX devices also provide a number of
new configuration enhancements that you can take advantage of when
migrating APEX II and APEX 20K designs to Stratix and Stratix GX
devices.
Configuration Speed & Schemes
You can configure Stratix and Stratix GX devices at a maximum clock
speed of 100 MHz, which is faster than the 66-MHz and 33-MHz
maximum configuration speeds for APEX II and APEX 20K devices,
respectively. Similar to APEX II devices, you can use 8-bit parallel data to
configure Stratix and Stratix GX devices (the target device can receive
byte-wide configuration data on each clock cycle) significantly speeding
up configuration times.
You can select a configuration scheme based on how the MSEL pins are
driven. Stratix and Stratix GX devices have three MSEL pins (APEX II and
APEX 20K devices have two MSEL pins) for determining the
configuration scheme.
Specifies the clock source for the input synchronization registers,
which can be either
when the Registered Inputs option is selected.
Indicates the fast PLL can be shared between receiver and transmitter
applications.
tx_inclock
Function
or
tx_coreclock
Note (1)
Altera Corporation
. Used only
July 2005