EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 646

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

10-Gigabit Ethernet
8–2
Stratix Device Handbook, Volume 2
The purpose of the 10-Gigabit Ethernet proposed standard is to extend
the operating speed to 10 Gbps defined by protocol IEEE 802.3 and
include WAN applications. These additions provide a significant increase
in bandwidth while maintaining maximum compatibility with current
IEEE 802.3 interfaces.
Since its inception in March 1999, the 10-Gigabit Ethernet Task Force has
been working on the IEEE 802.3ae Standard. Some of the information in
the following sections is derived from Clauses 46, 47, 49, and 51 of the
IEEE Draft P802.3ae/D3.1 document. A fully ratified standard is
expected in the first half of 2002.
10-Gigabit Ethernet to the Open Systems Interconnection (OSI) protocol
stack.
Figure 8–1. 10-Gigabit Ethernet Protocol in Relation to OSI Protocol Stack
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
LLC: logical link controller
MAC: media access controller
PCS: physical coding sublayer
PHY: physical layer
PMA: physical medium attachment
PMD: physical medium dependent
MDI: medium dependent interface
OSI Reference
Model Layers
Presentation
Application
Figure
Data Link
Transport
Network
Physical
Session
8–1:
Figure 8–1
XGMII
MDI (7)
XSBI
shows the relationship of
Reconciliation
Higher Layers
MAC (2)
PMA (5)
PMD (6)
Medium
PCS (3)
LLC (1)
Altera Corporation
July 2005
PHY (4)