EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 506

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

f
frequency)
(LVDS, LVPECL,
HyperTransport
technology)
f
f
operation
(LVDS, LVPECL,
HyperTransport
technology)
f
frequency)
(PCML)
f
HSCLK
HSCLK
HSDR
HSCLK
HSCLK
Table 5–7. High-Speed I/O Specifications for Flip-Chip Packages (Part 1 of 3)
Device
Symbol
(Clock
= f
(Clock
= f
HSDR
HSDR
/ W
/ W
W = 4 to 30
W = 2 (Serdes
bypass)
W = 2 (Serdes used)
W = 1 (Serdes
bypass)
W = 1 (Serdes used)
J = 10
J = 8
J = 7
J = 4
J = 2
J = 1 (LVDS and
LVPECL only)
W = 4 to 30 (Serdes
used)
W = 2 (Serdes
bypass)
W = 2 (Serdes used)
W = 1 (Serdes
bypass)
W = 1 (Serdes used)
Conditions
Tables 5–7
and
Min
150
100
300
300
300
300
300
100
100
150
100
300
10
50
10
50
5–8
-5 Speed Grade
show the high-speed I/O timing for Stratix devices
Typ
Max
210
231
420
462
717
840
840
840
840
462
462
100
200
200
250
400
Min
150
100
300
300
300
300
300
100
100
150
100
300
10
50
10
50
-6 Speed Grade
Typ
Notes
Max
210
231
420
462
717
840
840
840
840
462
462
100
200
200
250
400
(1),
Min
150
150
100
300
300
300
300
300
100
100
100
300
(2)
10
50
10
50
-7 Speed Grade
Typ
77.75
155.5
Max
156
231
312
462
624
640
640
640
640
640
640
150
200
311
Min
150
100
300
300
300
300
300
100
100
150
100
300
10
50
10
50
-8 Speed Grade
Typ
115.5
77.75
155.5
Max
231
231
462
462
462
462
462
462
462
462
150
200
311
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit