EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 496

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Differential I/O Interface & Fast PLLs
Figure 5–17. Fast PLL & Channel Layout in EP1S30 to EP1S80 Devices
Notes to
(1)
(2)
(3)
5–24
Stratix Device Handbook, Volume 2
Wire-bond packages only support up to 624-Mbps until characterization shows otherwise.
See
There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of
its bank quadrant (e.g., if PLL 2 clocks PLL 1’s channel region), those clocked channels support up to 840 Mbps.
Transmitter
Transmitter
Transmitter
Transmitter
FPLL7CLK
FPLL8CLK
Tables 5–10
Figure
Receiver
Receiver
Receiver
Receiver
CLKIN
CLKIN
5–17:
through
PLL 7
PLL 1
PLL 2
PLL 8
Fast
Fast
Fast
Fast
5–14
for the exact number of channels each package and device density supports.
(3)
Channels in 20 Rows (2)
Channels in 20 Rows (2)
Channels in 20 Rows (2)
Channels in 20 Rows (2)
Up to 20 Receiver and
Up to 20 Receiver and
Up to 20 Receiver and
Up to 20 Receiver and
20 Transmitter
20 Transmitter
20 Transmitter
20 Transmitter
(3)
Note (1)
PLL 10
PLL 4
PLL 3
PLL 9
Fast
Fast
Fast
Fast
Altera Corporation
FPLL10CLK
Transmitter
Receiver
Transmitter
Receiver
CLKIN
CLKIN
Transmitter
Receiver
Transmitter
Receiver
FPLL9CLK
July 2005