EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 771

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
July 2005
nSTATUS
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
N/A
User Mode
All
Configuration
Scheme
Bidirectional
open-drain
Pin Type
The device drives
after power-up and releases it after the POR
time.
Status output. If an error occurs during
configuration,
target device. Status input. If an external
source drives the
configuration or initialization, the target device
enters an error state.
Driving
initialization does not affect the configured
device. If a configuration device is used, driving
nSTATUS
to attempt to configure the FPGA, but since the
FPGA ignores transitions on
mode, the FPGA does not reconfigure. To
initiate a reconfiguration,
pulled low.
The enhanced configuration devices’ and
EPC2 devices’
internal programmable pull-up resistors. If
internal pull-up resistors on the enhanced
configuration device are used, external 10-k
pull-up resistors should not be used on these
pins. When using EPC2 devices, only external
10-k pull-up resistors should be used.
This pin uses Schmitt trigger input buffers.
Configuring Stratix & Stratix GX Devices
nSTATUS
Stratix Device Handbook, Volume 2
low causes the configuration device
nSTATUS
OE
Description
nSTATUS
nSTATUS
low after configuration and
and
(Part 3 of 8)
nCS
is pulled low by the
nCONFIG
pins have optional
nSTATUS
pin low during
low immediately
must be
in user-
11–53