EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 760

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Configuration Schemes
11–42
Stratix Device Handbook, Volume 2
f
For more information on the JRunner software driver, see the JRunner
Software Driver: An Embedded Solution to the JTAG Configuration White
Paper and zip file.
Jam STAPL Programming & Test Language
The Jam
standard JESD-71, is a standard file format for in-system
programmability (ISP) purposes. Jam STAPL supports programming or
configuration of programmable devices and testing of electronic systems,
using the IEEE 1149.1 JTAG interface. Jam STAPL is a freely licensed open
standard.
Connecting the JTAG Chain to the Embedded Processor
There are two ways to connect the JTAG chain to the embedded processor.
The most straightforward method is to connect the embedded processor
directly to the JTAG chain. In this method, four of the processor pins are
dedicated to the JTAG interface, saving board space but reducing the
number of available embedded processor pins.
Figure 11–23
chain to an existing bus through an interface PLD. In this method, the
JTAG chain becomes an address on the existing bus. The processor then
reads from or writes to the address representing the JTAG chain.
TM
Standard Test and Programming Language (STAPL), JEDEC
illustrates the second method, which is to connect the JTAG
Altera Corporation
July 2005