EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 702

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

PLLs & Clock Networks
PLLs & Clock
Networks
10–18
Stratix Device Handbook, Volume 2
f
Furthermore, the altmult_add and altmult_accum (MAC)
megafunctions are only available for Stratix and Stratix GX devices
because these megafunctions target Stratix and Stratix GX DSP blocks,
which are not available in other device families. If you attempt to use
these megafunctions in designs that target other Altera device families,
the Quartus II software reports an error message. Use lpm_mult and an
lpm_add_sub or an altaccumulate megafunction for similar
functionality in other device families.
If you use a third-party synthesis tool, you may be able to avoid the
megafunction conversion process. LeonardoSpectrum and Synplify
provide inference support for lpm_mult, altmult_add, and
altmult_accum (MAC) to use the DSP blocks.
If your design does not require you to implement all the multipliers in
DSP blocks, you must manually set a global parameter or a parameter for
each instance to force the tool to implement the lpm_mult megafunction
in LEs. Depending on the synthesis tools, inference of DSP blocks is
handled differently.
For more information about using DSP blocks in Stratix and Stratix GX
devices, see the DSP Blocks in Stratix & Stratix GX Devices chapter of the
Stratix Device Handbook.
Stratix and Stratix GX devices provide exceptional clock management
with a hierarchical clock network and up to four enhanced phase-locked
loops (PLLs) and eight fast PLLs versus the four general-purpose PLLs
and four True-LVDS
clock interfacing, numerous advanced clocking features, and significant
enhancements over APEX II and APEX 20K PLLs, the Stratix and
Stratix GX device PLLs increase system performance and bandwidth.
Clock Networks
There are 16 global clock networks available throughout each Stratix or
Stratix GX device as well as two fast regional and four regional clock
networks per device quadrant, resulting in up to 40 unique clock
networks per device. The increased number of dedicated clock resources
available in Stratix and Stratix GX devices eliminate the need to use
general-purpose I/O pins as clock inputs.
Stratix EP1S25 and smaller devices have 16 dedicated clock pins and
EP1S30 and larger devices have four additional clock pins to feed various
clocking networks. In comparison, APEX II devices have eight dedicated
clock pins and APEX 20KE and APEX 20KC devices have four dedicated
clock pins.
TM
PLLs in APEX II devices. By providing superior
Altera Corporation
July 2005