EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 597

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 7–11. Time & Frequency Domain Representations of Interpolation for I = 4
Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
As an example, CD players use interpolation, where the nominal sample
rate of audio input is 44.1 kilosamples per second. A typical
implementation might have an interpolation (oversampling) factor of 4
generating 176.4 kilosamples per second of oversampled data stream.
Polyphase Interpolation Filters
A direct implementation of an interpolation filter, as shown in
Figure
filter is 16 taps long and a multiplication takes one cycle, then the number
of computations required per cycle is 16 I. Depending on the
interpolation factor (I), this number can be quite big and may not be
achievable in hardware. A polyphase implementation of the low pass
filter can reduce the number of computations required per cycle, often by
a large factor, as will be evident later in this section.
The polyphase implementation “splits” the original filter into I
polyphase filters whose impulse responses are defined by the following
equation:
h
k
7–10, imposes a high computational burden. For example, if the
n
=
h k
+
nI
Stratix Device Handbook, Volume 2
7–19