EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 587

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 7–4. Quartus II Software View of MegaWizard Implementation of a DSP Block in Four-Multipliers
Adder Mode
Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Each input register of the DSP block provides a shiftout output that
connects to the shiftin input of the adjacent input register of the same DSP
block. The registers on the boundaries of a DSP block also connect to the
registers of adjacent DSP blocks through the use of shiftin/shiftout
connections. These connections create register chains spanning multiple
DSP blocks, which makes it easy to increase the length of FIR filters.
Figure 7–5
Filters with more taps can be implemented by connecting DSP blocks in
a similar manner, provided sufficient DSP blocks are available in the
device.
1
The input data can be fed directly or by using the shiftout/shiftin chains,
which allow a single input to shift down the register chain inside the DSP
block. The input to each of the registers has a multiplexer, hence, the data
can be fed either from outside the DSP block or the preceding register.
This can be selected from the MegaWizard
as shown in
shiftout/shiftin flip-flop chains where the multiplexers are configured to
use these chains. In this example, the flip-flops inside the DSP blocks
serve as the taps of the FIR filter.
Adding the outputs of the two DSP blocks requires an external
adder which can be implemented using logic cells.
shows two DSP blocks connected to create an 8-tap FIR filter.
Figure
7–4. The example in
Stratix Device Handbook, Volume 2
Figure 7–5
®
in the Quartus
uses the
®
II software,
7–9