EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 525

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
July 2005
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One fast PLL can drive the 20 transmitter channels and 20 receiver
channels closest to it with data rates of up to 840 Mbps. Wire-bond
packages support a data rate of 624 Mbps. The corner fast PLLs in EP1S80
devices support data rates of up to 840 Mbps. See
5–14
Stratix device density and package.
Since the fast PLL drives the 20 closest differential channels, there are
coverage overlaps in the EP1S30 and larger devices that have two fast
PLLs per I/O bank. In these devices, either the center fast PLL or the
corner fast PLL can drive the differential channels in the middle of the
I/O bank.
Fast PLLs can drive more than 20 transmitter and 20 receiver channels
(see
of channels each PLL can drive). In addition, the center fast PLLs can
drive either one I/O bank or both I/O banks on the same side (left or
right) of the device, while the corner fast PLLs can only drive the
differential channels in its I/O bank. Neither fast PLL can drive the
differential channels in the opposite side of the device.
The center fast PLLs can only drive two I/O at 840 Mbps. For example,
EP1S20 device fast PLL 1 can drive all 33 differential channels on its side
(17 channels from I/O bank 2 and 16 channels from I/O bank 1) running
at 840 Mbps in 4
on the same side of the device, the other center fast PLL cannot drive any
differential channels on the device.
See
one fast PLL can drive. The number of channels is also listed in the
Quartus II software. The Quartus II software gives an error message if
you try to compile a design exceeding the maximum number of channels.
Additional high-speed DIFFIO pin information for Stratix devices is
available in Volume 3 of the Stratix Device Handbook.
Tables 5–10
Tables 5–10
for the number of high-speed differential channels in a particular
through
×
through
mode. When a center fast PLL drives the opposite bank
High-Speed Differential I/O Interfaces in Stratix Devices
5–14
5–14
for the maximum number of channels that
and
Figures
Stratix Device Handbook, Volume 2
5–16, and
Tables 5–10
5–17
for the number
through
5–53