EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 379

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Figure 2–5. Simple Dual-Port Timing Waveforms
Note to
(1)
Altera Corporation
July 2005
asynch_data_out
synch_data_out
wraddress
rdaddress
The rden signal is not available in the M-RAM block. A M-RAM block in simple dual-port mode is always reading
out the data stored at the current read address location.
wrclock
data_in
rdclock
wren
rden
Figure
doutn-2
2–5:
din-1
an-1
doutn-1
bn
an
din
M-RAM blocks have one write enable signal in simple dual-port mode. To
perform a write operation, the write enable is held high. The M-RAM
block is always enabled for read operation. If the read address and the
write address select the same address location during a write operation,
the M-RAM block output is unknown.
Figure 2–5
simple dual-port mode.
Implementing True Dual-Port Mode
M4K and M-RAM blocks offer a true dual-port mode to support any
combination of two-port operations: two reads, two writes, or one read
and one write at two different clock frequencies.
true dual-port memory configuration for TriMatrix memory.
doutn-1
doutn
a0
b0
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
shows timing waveforms for read and write operations in
a1
Note (1)
doutn
dout0
a2
b1
a3
Stratix Device Handbook, Volume 2
dout0
din4
a4
b2
Figure 2–6
din5
a5
shows the
b3
din6
2–11
a6