UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 100

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

5.5 Operation of Clock Generator
standby mode.
mode register (SCKM), and subclock control register (CSS), as follows.
98
The clock generator generates the following clocks and controls the operation modes of the CPU, such as the
The operation of the clock generator is determined by the processor clock control register (PCC), suboscillation
Main system clock
Subsystem clock
CPU clock
Clock to peripheral hardware
(a)
(b)
(c)
(d)
(e)
(f)
The slow mode (1.6 s at 5.0 MHz operation) of the main system clock is selected when the RESET
signal is generated (PCC = 02H). While a low level is being input to the RESET pin, oscillation of the
main system clock is stopped.
Three types of minimum instruction execution time (0.4 s and 1.6 s main system clock (at 5.0 MHz
operation), 122 s subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM, and
CSS settings.
Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system
where no subsystem clock is used, setting bit 1 (FRC) of SCKM so that the on-chip feedback resistor
cannot be used reduces current consumption in the STOP mode. In a system where a subsystem clock
is used, setting bit 0 of SCKM to 1 can cause the subsystem clock to stop oscillation.
Bit 4 (CSS0) of CSS can be used to select the subsystem clock so that low current consumption
operation is used (at 122 s, 32.768 kHz operation).
With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating by
setting bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot.
The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system
clock.
controller/driver only. As a result, 8-bit timer 02 (when watch timer output is selected for the count clock
when the subsystem clock is running) and the watch function can continue running even in the standby
mode. The other hardware stops when the main system clock stops, because it runs based on the main
system clock (except for external input clock pulses).
f
CPU
The subsystem clock pulse is supplied to 8-bit timer 02, the watch timer, and the LCD
f
XT
f
X
CHAPTER 5 CLOCK GENERATOR
User’s Manual U13952EJ3V1UD