UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 113

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

6.4.4 16-bit timer counter 50 readout
value, the buffer operation is held pending at the CPU clock falling edge after the read signal of the TM50 lower byte
rises, and the count value is retained. The 16-bit counter read buffer value in the retention state can be read out as
the count value.
falls.
The count value of 16-bit timer counter 50 (TM50) is read out by a 16-bit manipulation instruction.
TM50 readout is performed via a 16-bit counter read buffer. The 16-bit counter read buffer latches the TM50 count
Cancellation of pending is performed at the CPU clock falling edge after the read signal of the TM50 higher byte
RESET input sets TM50 to 0000H and then to free-running mode again.
Figure 6-10 shows the timing of 16-bit timer counter 50 readout.
Cautions 1. The count value after releasing stop becomes undefined because the count operation is
16-bit counter read buffer
TM50 read signal
2. AIthough TM50 is manipulated by a 16-bit transfer instruction, 8-bit transfer instruction can
3. When using an 8-bit transfer instruction, execute in order from lower byte to higher byte in
executed during the oscillation stabilization time.
also be used.
When using an 8-bit transfer instruction, execute by direct addressing.
pairs. If the only lower byte is read, the pending state of the 16-bit counter read buffer is not
canceled, and if the only higher byte is read, an undefined count value is read.
Count clock
CPU clock
TM50
Figure 6-10. Readout Timing of 16-Bit Timer Counter 50
0000H
0000H
CHAPTER 6 16-BIT TIMER 50
User’s Manual U13952EJ3V1UD
0001H
0001H
N
Read signal latch
prohibited period
N
N + 1
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