UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 275

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CMP
ADDW
SUBW
CMPW
INC
DEC
INCW
DECW
ROR
ROL
RORC
ROLC
SET1
CLR1
SET1
CLR1
NOT1
Mnemonic
Remark
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
AX, #word
AX, #word
AX, #word
r
saddr
r
saddr
rp
rp
A, 1
A, 1
A, 1
A, 1
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
Operands
CHAPTER 20 INSTRUCTION SET
Bytes
User’s Manual U13952EJ3V1UD
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
2
3
2
3
3
2
3
2
1
1
1
Clocks
10
10
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
6
6
4
6
6
6
4
6
2
2
2
A
(saddr)
A
A
A
A
A
AX, CY
AX, CY
AX
r
(saddr)
r
(saddr)
rp
rp
(CY, A
(CY, A
(CY
(CY
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
CY
CY
CY
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
r + 1
r
word
rp + 1
rp
7
0
1
0
CY
A
A
1
1
0
0
7
1
0
byte
, A
, A
CPU
1
(saddr) + 1
(saddr)
AX + word
AX
A
A
1
0
1
0
0
7
7
0
, A
, A
) selected by the processor clock control
1
0
m 1
m+1
word
CY, A
CY, A
Operation
1
A
A
m 1
m+1
m
m
)
)
1
1
A
A
m
m
)
)
1
1
Z AC CY
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Flag
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
273
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x