UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 102

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

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5.6.2 Switching between system clock and CPU clock
100
Interrupt request signal
The following figure illustrates how the CPU clock and system clock are switched.
<1> The CPU is reset when the RESET pin is made low on power application. Reset is released when the
<2> After the time required for the V
<3> A drop of the V
<4> Recovery of the V
Caution
RESET pin is later made high, and the main system clock starts oscillating. At this time, the oscillation
stabilization time (2
After that, the CPU starts instruction execution at the low speed of the main system clock (1.6
5.0 MHz operation).
has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock
control register (CSS) are rewritten so that the high-speed operation can be selected.
clock (at this moment, the subsystem clock must be in the stable oscillation status).
the main system clock starts oscillating. After the time required for the oscillation to stabilize has elapsed,
PCC1 and CSS0 are rewritten so that high-speed operation can be selected again.
System clock
CPU clock
RESET
V
When the main system clock is stopped and the device is operating on the subsystem
clock, wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.
DD
DD
Figure 5-8. Switching Between System Clock and CPU Clock
voltage is detected by an interrupt request signal. The clock is switched to the subsystem
DD
15
/f
voltage is detected by an interrupt request signal. Bit 7 (MCC) of PCC is set to 0, and
X
) is automatically secured.
DD
CHAPTER 5 CLOCK GENERATOR
voltage to rise to the level at which the CPU can operate at the high speed
Low-speed
operation
User’s Manual U13952EJ3V1UD
Wait (6.55 ms: at 5.0 MHz operation)
Internal reset operation
f
X
High-speed
operation
f
X
Subsystem clock
operation
f
XT
High-speed
operation
f
X
s at