UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 13

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CHAPTER 4 PORT FUNCTIONS........................................................................................................... 70
CHAPTER 5 CLOCK GENERATOR ...................................................................................................... 89
3.3 Instruction Address Addressing................................................................................................. 61
3.4 Operand Address Addressing .................................................................................................... 64
4.1 Function of Port............................................................................................................................ 70
4.2 Configuration of Ports ................................................................................................................. 72
4.3 Registers Controlling Ports......................................................................................................... 85
4.4 Operation of Ports ........................................................................................................................ 88
5.1 Functions of Clock Generator..................................................................................................... 89
5.2 Configuration of Clock Generator .............................................................................................. 89
5.3 Registers Controlling Clock Generator...................................................................................... 91
5.4 System Clock Oscillators ............................................................................................................ 94
5.5 Operation of Clock Generator ..................................................................................................... 98
5.6 Changing Setting of System Clock and CPU Clock.................................................................. 99
3.2.2 General-purpose registers................................................................................................................. 57
3.2.3 Special function registers (SFR)........................................................................................................ 58
3.3.1 Relative addressing........................................................................................................................... 61
3.3.2 Immediate addressing ....................................................................................................................... 62
3.3.3 Table indirect addressing .................................................................................................................. 63
3.3.4 Register addressing .......................................................................................................................... 63
3.4.1 Direct addressing .............................................................................................................................. 64
3.4.2 Short direct addressing ..................................................................................................................... 65
3.4.3 Special function register (SFR) addressing ....................................................................................... 66
3.4.4 Register addressing .......................................................................................................................... 67
3.4.5 Register indirect addressing.............................................................................................................. 68
3.4.6 Based addressing ............................................................................................................................. 69
3.4.7 Stack addressing............................................................................................................................... 69
4.2.1 Port 0 ................................................................................................................................................ 72
4.2.2 Port 2 ................................................................................................................................................ 73
4.2.3 Port 4 ................................................................................................................................................ 78
4.2.4 Port 5 ................................................................................................................................................ 80
4.2.5 Port 6 ................................................................................................................................................ 81
4.2.6 Port 8 ................................................................................................................................................ 83
4.2.7 Port 9 ................................................................................................................................................ 84
4.4.1 Writing to I/O port .............................................................................................................................. 88
4.4.2 Reading from I/O port........................................................................................................................ 88
4.4.3 Arithmetic operation of I/O port ......................................................................................................... 88
5.4.1 Main system clock oscillator.............................................................................................................. 94
5.4.2 Subsystem clock oscillator ................................................................................................................ 95
5.4.3 Examples of incorrect resonator connection ..................................................................................... 96
5.4.4 Divider............................................................................................................................................... 97
5.4.5 When no subsystem clock is used .................................................................................................... 97
5.6.1 Time required for switching between system clock and CPU clock................................................... 99
5.6.2 Switching between system clock and CPU clock ............................................................................ 100
User’s Manual U13952EJ3V1UD
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