UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 273

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

MOVW
XCHW
ADD
ADDC
SUB
Mnemonic
Note Only when rp = BC, DE, or HL.
Remark
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
rp, #word
AX, saddrp
saddrp, AX
AX, rp
rp, AX
AX, rp
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
Note
Note
Note
Operands
CHAPTER 20 INSTRUCTION SET
Bytes
User’s Manual U13952EJ3V1UD
3
2
2
1
1
1
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
Clocks
6
6
8
4
4
8
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
rp
AX
(saddrp)
AX
rp
AX
A, CY
(saddr), CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
(saddr), CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
(saddr), CY
A, CY
A, CY
A, CY
A, CY
A, CY
word
AX
(saddrp)
rp
rp
A + byte
A + r
A + (saddr)
A + (addr16)
A + (HL)
A + (HL + byte)
A + byte + CY
A + r + CY
A + (saddr) + CY
A + (addr16) + CY
A + (HL) + CY
A + (HL + byte) + CY
A
A
A
A
A
A
CPU
AX
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
) selected by the processor clock control
(saddr) + byte
(saddr) + byte + CY
(saddr)
Operation
byte
Z AC CY
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Flag
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
271
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x