UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 60

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.2.3 Special function registers (SFR)
manipulation instructions. The manipulatable bit unit (1, 8, or 16) differs depending on the special function register
type.
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Unlike a general-purpose register, each special function register has a special function.
SFRs are allocated in the 256-byte area FF00H to FFFFH.
A special function register can be manipulated, like a general-purpose register, using operation, transfer, and bit
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
• 8-bit manipulation
• 16-bit manipulation
Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows:
• Symbol
• R/W
• Manipulatable bit unit
• After reset
Describes a symbol reserved by assembler for the 1-bit manipulation instruction operand (sfr.bit).
manipulation can also be specified by an address.
Describes a symbol reserved by assembler for the 8-bit manipulation instruction operand (sfr).
manipulation can also be specified by an address.
Describes a symbol reserved by assembler for the 16-bit manipulation instruction operand. When addressing an
address, describe an even address.
Indicates the address of the special function register. The symbols shown in this column are reserved words in
the assembler, and have been defined in the header file named “sfrbit.h” in the C compiler. Therefore, these
symbols can be used as instruction operands if an assembler or integrated debugger is used.
Indicates whether the special function register in question can be read or written.
R/W: Read/write
R:
W:
Indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated.
Indicates the status of the special function register when the RESET signal is input.
Read only
Write only
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U13952EJ3V1UD
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