UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 243

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

execution, n clocks (n = 4 to 10), are n
completion of the instruction under execution. Figure 15-13 shows an example using the 8-bit data transfer instruction
MOV A, r. Because this instruction is executed in 4 clocks, if an interrupt request is generated between the start of
execution and the 3rd clock, interrupt request acknowledgment processing will take place following the completion of
MOV A, r.
acknowledgment processing will begin after execution of the next instruction is complete.
instruction). In this case, the interrupt request will be processed after execution of MOV A, r, which follows NOP, is
complete.
15.4.3 Multiple interrupt servicing
multiple interrupt servicing.
request). The other interrupt request is disabled (IE = 0) at the time when an interrupt request is acknowledged.
Therefore, it is necessary to set (1) the IE flag to realize the interrupt enable state using an EI instruction during
interrupt request servicing in order to enable multiple interrupt servicing.
Interrupt request
If the interrupt request has generated an interrupt request flag (XXIF) by the time the instruction clocks under
If the interrupt request flag (XXIF) is generated in the final clock of the instruction, interrupt request
Figure 15-14 shows an example whereby an interrupt request was generated in the 2nd clock of NOP (a 2-clock
Caution When interrupt request flag registers 0 and 1 (IF0 and IF1) or interrupt mask flag registers 0 and
Interrupt request
Processing in which another interrupt request is acknowledged while an interrupt request is serviced is called
Multiple interrupts are not performed unless an interrupt request is enabled (IE = 1) (except non-maskable interrupt
CPU
Figure 15-14. Interrupt Request Acknowledgment Timing
Clock
Clock
CPU
1 (MK0 and MK1) are being accessed, interrupt requests will be held pending.
Figure 15-13. Interrupt Request Acknowledgment Timing (Example: MOV A, r)
(When Interrupt Request Flag Is Generated in Final Clock Under Execution)
NOP
MOV A, r
CHAPTER 15 INTERRUPT FUNCTIONS
1, interrupt request acknowledgment processing will start following the
User’s Manual U13952EJ3V1UD
MOV A, r
Saving PSW and PC, and
jump to interrupt servicing
8 clocks
Saving PSW and PC, and
jump to interrupt servicing
Interrupt servicing program
8 clocks
Interrupt servicing
program
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