UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 114

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

6.5 Cautions on Using 16-Bit Timer 50
6.5.1 Restrictions when rewriting 16-bit compare register 50
112
(1)
(2)
<Countermeasure A> When rewriting using 8-bit access
<1> Disable interrupts (TMMK50 = 1) and the inversion control of timer output (TOC50 = 0).
<2> First rewrite the higher 1 byte of CR50 (16 bits).
<3> Then rewrite the lower 1 byte of CR50 (16 bits).
<4> Clear the interrupt request flag (TMIF50).
<5> Enable timer interrupts/timer output inversion after half a cycle or more of the count clock has elapsed from
<Program example A> (count clock = 32/f
TM50_VCT: SET1 TMMK50
Note Because the INTTM50 signal becomes high level for half a cycle of the count clock after an interrupt is
Disable interrupts (TMMK50 = 1) and the inversion control of timer output (TOC50 = 0) before rewriting the
compare register (CR50).
If CR50 is rewritten with interrupts enabled, an interrupt request may be generated immediately.
Depending on the timing of rewriting the compare register (CR50), the interval time may become twice as
long as the intended time. Similarly, a shorter waveform or twice-longer waveform than the intended timer
output waveform may be output.
To avoid this problem, rewrite the compare register using either of the following procedures.
the beginning of the interrupt.
generated, the output is inverted if TOC50 is set to 1 during this period.
CLR1 TMC50.3
MOV
MOV
MOV
MOV
CLR1 TMIF50
CLR1 TMMK50
SET1 TMC50.3
A,#xxH
!0FF17H,A ; Rewrite CR50 higher byte (8 clocks)
A,#yyH
!0FF16H,A ; Rewrite CR50 lower byte (8 clocks)
; Disable timer interrupts (6 clocks)
; Disable timer output inversion (6 clocks)
; Set the rewrite value of higher byte (6 clocks)
; Set the rewrite value of lower byte (6 clocks)
; Clear interrupt request flag (6 clocks)
; Enable timer interrupts (6 clocks)
; Enable timer output inversion
CHAPTER 6 16-BIT TIMER 50
User’s Manual U13952EJ3V1UD
X
, CPU clock = f
X
)
Total: 16 clocks or
more
Note