UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 112

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

6.4.3 Capture operation
register in synchronization with a capture trigger.
latches and retains the count value of 16-bit timer counter 50 (TM50). TCP50 fetches the count value within 2 clocks
and retains the count value until the next capture edge detection.
16-bit counter read buffer
110
TMC50
In a capture operation, the count value of 16-bit timer counter 50 (TM50) is captured and latched to the capture
Set as shown in Figure 6-8 to allow the 16-bit timer to start a capture operation.
16-bit capture register 50 (TCP50) starts a capture operation after the CPT5 capture trigger edge is defected, and
Table 6-3 and Figure 6-9 shows the settings of the capture edge and the capture operation timing, respectively.
Caution Because TCP50 is rewritten when a capture trigger edge is detected during TCP50 read, disable
TOD50 TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50
CPT501
–
Count clock
0
0
1
1
Figure 6-8. Settings of 16-Bit Timer Mode Control Register 50 for Capture Operation
capture trigger edge detection during TCP50 read.
TCP50
0/1
Figure 6-9. Capture Operation Timing (Both Edges of CPT5 Pin Are Specified)
TM50
CPT5
0/1
0/1
0000H
0000H
CPT500
0/1
0
1
0
1
0001H
0001H
Table 6-3. Settings of Capture Edge
Undefined
0
CHAPTER 6 16-BIT TIMER 50
User’s Manual U13952EJ3V1UD
0/1
Capture operation prohibited
CPT5 pin rising edge
CPT5 pin falling edge
CPT5 pin both edges
0/1
Capture edge detection
Count clock selection
Capture edge selection (see Table 6-3)
Capture start
N
N
Capture Edge Selection
N
M – 1
Capture edge detection
Capture start
M
M
M