UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 251

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

16.2.2 STOP mode
Main system clock generator
CPU
Port (output latch)
16-bit timer (TM50)
8-bit timer/event counter
(TM00 and TM01)
8-bit timer (TM02)
Watch timer
Watchdog timer
Serial interface
A/D converter
LCD controller/driver
Comparator
External interrupt
(1)
The operation status in the STOP mode is shown in the following table.
Notes 1. Operation is enabled only when TI0 or TI1 is selected as the count clock.
Setting and operation status of STOP mode
The STOP mode is set by executing the STOP instruction.
Caution Because the standby mode can be released by an interrupt request signal, the standby
2. Operation is enabled while the subsystem clock is selected.
3. Operation is enabled in both 3-wire serial I/O and UART modes while an external clock is being used.
4. Maskable interrupt that is not masked
5. Operation is enabled while TM02 is running.
6. Operation is enabled as an external interrupt.
Item
mode is released as soon as it is set if there is an interrupt source whose interrupt request
flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the
HALT mode is set immediately after the STOP instruction has been executed, the wait time
set by the oscillation stabilization time selection register (OSTS) elapses, and then an
operation mode is set.
While the subsystem clock is running
Oscillation stopped
Operation stopped
Remains in the state existing before the selection of STOP mode.
Operation stopped
Operation enabled
Operation enabled
Operation enabled
Operation stopped
Operation enabled
Operation stopped
Operation enabled
Operation enabled
Operation enabled
Table 16-3. STOP Mode Operating Status
CHAPTER 16 STANDBY FUNCTION
STOP Mode Operation Status While Main System Clock Is Running
User’s Manual U13952EJ3V1UD
Note 1
Note 2
Note 2
Note 3
Note 2
Notes 5, 6
Note 4
While the subsystem clock is not running
Operation stopped
Operation stopped
Operation stopped
Operation enabled
Note 6
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