UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 203

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

INTCSI00
(2)
(3)
SCK
Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units.
transmitted/received bit by bit in synchronization with the serial clock.
Transmit shift register 00 (TXS00/SIO00) and receive shift register 00 (RXS00) shift operations are
performed in synchronization with the fall of the serial clock (SCK). Then transmit data is held in the SO latch
and output from the SO pin. Also, receive data input to the SI pin is latched in receive buffer register 00
(RXB00/SIO00) on the rise of SCK.
At the end of an 8-bit transfer, the operation of TXS00/SIO00 or RXS00 stops automatically, and the interrupt
request signal (INTCSI00) is generated.
Transfer start
Serial transfer is started by setting transfer data to transmit shift register 00 (TXS00/SIO00) when the
following two conditions are satisfied.
Caution If CSIE00 is set to 1 after data is written to TXS00/SIO00, transfer does not start.
Termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal
(INTCSI00).
SO
SI
Bit 7 (CSIE00) of serial operation mode register 00 (CSIM00) = 1
Internal serial clock is stopped or SCK is a high level after 8-bit serial transfer.
1
Figure 13-11. 3-Wire Serial I/O Mode Timing
DO7
DI7
Transfer start at the falling edge of SCK
CHAPTER 13 SERIAL INTERFACE 00
2
DO6
DI6
User’s Manual U13952EJ3V1UD
3
DO5
DI5
4
DO4
DI4
5
DO3
DI3
6
DO2
DI2
7
DO1
DI1
End of transfer
8
DI0
DO0
Data is
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