UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 18

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure No.
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
16
Pin I/O Circuits .............................................................................................................................................42
Memory Map ( PD789405A and PD789415A)...........................................................................................44
Memory Map ( PD789406A and PD789416A)...........................................................................................45
Memory Map ( PD789407A and PD789417A)...........................................................................................46
Memory Map ( PD78F9418A)......................................................................................................................47
Data Memory Addressing ( PD789405A and PD789415A) .......................................................................50
Data Memory Addressing ( PD789406A and PD789416A) .......................................................................51
Data Memory Addressing ( PD789407A and PD789417A) .......................................................................52
Data Memory Addressing ( PD78F9418A) ..................................................................................................53
Program Counter Configuration....................................................................................................................54
Program Status Word Configuration.............................................................................................................54
Stack Pointer Configuration..........................................................................................................................56
Data Saved to Stack Memory.......................................................................................................................56
Data Restored from Stack Memory ..............................................................................................................56
General-Purpose Register Configuration......................................................................................................57
Port Types ....................................................................................................................................................70
Block Diagram of P00 to P03 .......................................................................................................................72
Block Diagram of P20...................................................................................................................................73
Block Diagram of P21...................................................................................................................................74
Block Diagram of P22 and P24 ....................................................................................................................75
Block Diagram of P23...................................................................................................................................76
Block Diagram of P25 to P27 .......................................................................................................................77
Block Diagram of P40 to P45 .......................................................................................................................78
Block Diagram of P46 and P47 ....................................................................................................................79
Block Diagram of P50 to P53 .......................................................................................................................80
Block Diagram of P60 and P61 ....................................................................................................................81
Block Diagram of P62 to P66 .......................................................................................................................82
Block Diagram of P80 to P87 .......................................................................................................................83
Block Diagram of P90 to P93 .......................................................................................................................84
Format of Port Mode Register ......................................................................................................................86
Format of Pull-Up Resistor Option Register 0 ..............................................................................................86
Format of Pull-Up Resistor Option Register 1 ..............................................................................................87
Format of Pull-Up Resistor Option Register 2 ..............................................................................................87
Block Diagram of Clock Generator ...............................................................................................................90
Format of Processor Clock Control Register ................................................................................................91
Format of Suboscillation Mode Register.......................................................................................................92
Format of Subclock Control Register............................................................................................................93
External Circuit of Main System Clock Oscillator..........................................................................................94
External Circuit of Subsystem Clock Oscillator.............................................................................................95
Examples of Incorrect Resonator Connection ..............................................................................................96
Switching Between System Clock and CPU Clock .....................................................................................100
LIST OF FIGURES (1/5)
User’s Manual U13952EJ3V1UD
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