UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 170

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UPD78F9418AGK-9EU

Manufacturer Part Number
UPD78F9418AGK-9EU
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F9418AGK-9EU

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12.3 Register Controlling Comparator
168
CMPRM0
The comparator is controlled by the following register.
(1)
Note Bit 0 is read-only.
Cautions 1. Bits 4 to 7 must be fixed to 0.
Symbol
Comparator mode register 0 (CMPRM0)
CMPRM0 controls the power supply and clock output of the comparator. It also selects an open-drain output
for the comparator.
CMPRM0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CMPRM0 to 00H.
CMPON0
OPDR0
CMPOUT0
SELCMP0
2. If the comparator is enabled (CMPON0 = 1), noise may be induced. If it is necessary to
3. Similarly, if it is necessary to direct the output of the comparator to the port, enable the
0
0
1
0
1
0
1
7
generate an interrupt request signal (INTCMP0) from the output of the comparator, enable the
comparator (CMPON0 = 1), then clear the interrupt request flag (CMPIF0) to 0, before
enabling interrupts.
comparator (CMPON0 = 1) in advance.
Comparator power supply off
Comparator power supply on
8-bit timer 02 (TM02) output
8-bit timer counter 02 (TM02) output if CMPREF0 > CMPIN0
CMOS output
N-ch open-drain output
The comparator output is read.
6
0
5
0
Figure 12-2. Format of Comparator Mode Register 0
0
4
CMPON0 SELCMP0 OPDR0 CMPOUT0
3
CHAPTER 12 COMPARATOR
User’s Manual U13952EJ3V1UD
2
Comparator power supply on/off control
1
Open-drain output selection
Clock output control
0
Address
FF4EH
After reset
00H
R/W
R/W
Note

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