UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 274

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

272
SUBC
AND
OR
XOR
Mnemonic
Remark
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
A, #byte
saddr, #byte
A, r
A, saddr
A, !addr16
A, [HL]
A, [HL+byte]
Operands
CHAPTER 20 INSTRUCTION SET
Bytes
User’s Manual U13952EJ3V1UD
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
Clocks
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
A, CY
(saddr), CY
A, CY
A, CY
A, CY
A, CY
A, CY
A
(saddr)
A
A
A
A
A
A
(saddr)
A
A
A
A
A
A
(saddr)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A V byte
A V r
A V (saddr)
A V (addr16)
A V (HL)
A V (HL + byte)
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
A
A
A
A
A
A (HL + byte)
CPU
(saddr)
(saddr)
(saddr) V byte
byte
r
(saddr)
(addr16)
(HL)
) selected by the processor clock control
(saddr)
CY
Operation
CY
CY
byte
byte
CY
CY
byte
CY
CY
Z AC CY
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Flag
x
x
x
x
x
x
x
x
x
x
x
x
x
x