UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 93

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

5.3 Registers Controlling Clock Generator
The clock generator is controlled by the following registers.
(1)
Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control
Cautions 1. Bits 0 and 2 to 6 must be fixed to 0.
Remarks 1. f
Symbol
PCC
Processor clock control register (PCC)
Suboscillation mode register (SCKM)
Subclock control register (CSS)
Processor clock control register (PCC)
PCC selects the CPU clock and sets the division ratio.
PCC is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
register (PCC) and the CSS0 flag in the subclock control register (CSS). See 5.3 (3) Subclock control
register (CSS).
CSS0
MCC
MCC
7
0
1
0
0
1
1
2. The MCC bit can be set only when the subsystem clock has been selected as the CPU clock.
2. f
PCC1
Operation enabled
Operation disabled
X
XT
:
6
0
0
1
0
1
: Subsystem clock oscillation frequency
Main system clock oscillation frequency
f
f
f
5
0
X
X
XT
/2
/2
2
Figure 5-2. Format of Processor Clock Control Register
Selection of CPU clock (f
4
0
3
0
CHAPTER 5 CLOCK GENERATOR
Control of main system clock oscillator operation
2
0
User’s Manual U13952EJ3V1UD
PCC1
1
CPU
)
Note
0
0
Address
FFFBH
0.4 s
1.6 s
122 s
f
Minimum instruction execution time: 2/f
X
= 5.0 MHz or f
After reset
02H
XT
= 32.768 kHz operation
R/W
R/W
CPU
91