UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 197

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Parity error
Framing error
Overrun error
Receive Errors
(e)
RxD (input)
RxD (input)
INTSR00
INTSR00
Receive errors
The following three errors may occur during a receive operation: a parity error, framing error, or overrun
error. The data reception result error flag is set in asynchronous serial interface status register 00
(ASIS00). Receive error causes are shown in Table 13-7.
What kind of error occurred during reception can be judged by reading the contents of ASIS00 in the
receive error interrupt servicing (see Figures 13-9 and 13-10).
The contents of ASIS00 are reset (0) by reading receive buffer register 00 (RXB00) or receiving the next
data (if there is an error in the next data, the corresponding error flag is set).
Cautions 1. The contents of the ASIS00 register are reset (0) by reading receive buffer register
2. Be sure to read receive buffer register 00 (RXB00) even if a receive error occurs. If
00 (RXB00) or receiving the next data. To ascertain the error contents, read ASIS00
before reading RXB00.
RXB00 is not read, an overrun error will occur when the next data is received, and
the receive error state will continue indefinitely.
The parity specified at transmission and the reception data parity do not match.
A stop bit is not detected.
Reception of the next data is completed before data is read from the receive buffer register.
Start
Start
CHAPTER 13 SERIAL INTERFACE 00
Figure 13-10. Receive Error Timing
Table 13-7. Receive Error Causes
(b) Framing error or overrun error occurs
D0
D0
User’s Manual U13952EJ3V1UD
D1
D1
(a) Parity error occurs
D2
D2
Cause
D6
D6
D7
D7
Parity
Parity
Stop
Stop
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