UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 111

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

6.4.2 Operation as timer output
the interval set in TCL501 and TCL500.
TO5/INTP2/P26 pin is inverted. This enables timer output. At that time, TM50 counting continues and an interrupt
request signal (INTTM50) is generated.
TM50 count value
Timer outputs are repeatedly generated at the count value set to 16-bit compare register 50 (CR50) in advance at
To operate 16-bit timer as a timer output, the following settings are required.
Caution
When the count value of 16-bit timer counter 50 (TM50) matches the value set in CR50, the output status of the
Figure 6-7 shows the timing of timer output (see Table 6-2 for the interval time of 16-bit timer 50).
Note The TO5 initial value becomes low level when output is enabled (TOE50 = 1).
Remark
Count clock
Set P26 to output mode (PM26 = 0)
Set the output latch of P26 to 0
Set the count value to CR50
Set 16-bit timer mode control register 50 (TMC50) as shown in Figure 6-6
INTTM50
TO5
TOF50
TMC50
CR50
Figure 6-6. Settings of 16-Bit Timer Mode Control Register 50 for Timer Output Operation
Note
N = 0000H to FFFFH
If both the CPT501 flag and CPT500 flag are set to 0, the capture edge becomes operation
prohibited.
TOD50 TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50
–
0000H
t
0/1
N
0001H
0/1
0/1
Figure 6-7. Timer Output Timing
CHAPTER 6 16-BIT TIMER 50
User’s Manual U13952EJ3V1UD
1
N
N
Interrupt acknowledged
0
0/1
FFFFH 0000H 0001H
1
Overflow flag set
N
TO5 output enable
Setting of count clock (see Table 6-2)
Inverse enable of timer output data
N
N
Interrupt acknowledged
N
FFFFH
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