UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 99

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

5.4.4 Divider
5.4.5 When no subsystem clock is used
handle the XT1 and XT2 pins as follows:
when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the suboscillation mode register (SCKM) so
that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as stated above.
Remark
Caution If the X1 wire is parallel with the XT2 wire, crosstalk noise may occur between X1 and XT2,
The divider divides the output of the main system clock oscillator (f
If a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation,
XT1: Connect directly to V
XT2: Leave open
In this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator
When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect resistors
to the XT2 side in series.
resulting in a malfunction.
To avoid this, do not place the X1 and XT2 wires in parallel.
(e) Signal is fetched
V
V
SS0
SS1
,
Figure 5-7. Examples of Incorrect Resonator Connection (2/2)
X1
SS0
or V
X2
SS1
CHAPTER 5 CLOCK GENERATOR
User’s Manual U13952EJ3V1UD
(f) Signal lines of main system clock and subsystem
clock are parallel and close together
V
V
SS0
SS1
,
X
) to generate various clocks.
X2
XT2 is wired parallel to X1.
X1
XT2
XT1
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