UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 140

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

9.4 Operation of Watchdog Timer
9.4.1 Operation as watchdog timer
(WDTM) is set to 1.
to TCL22) of timer clock selection register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is
started. Set RUN to 1 within the set program loop detection time interval after the watchdog timer has been started.
By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the program
loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the value of bit 3
(WDTM3) of WDTM.
before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.
138
The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register
The count clock (program loop detection time interval) of the watchdog timer can be selected by bits 0 to 2 (TCL20
The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
Cautions 1. The actual program loop detection time may be up to 0.8% shorter than the set time.
TCL22
f
X
0
0
1
1
: Main system clock oscillation frequency
2. When the subsystem clock is selected as the CPU clock, the watchdog timer stops counting.
TCL21
0
1
0
1
Table 9-4. Program Loop Detection Time of Watchdog Timer
TCL20
0
0
0
0
2
2
2
2
CHAPTER 9 WATCHDOG TIMER
11
13
15
17
Program Loop Detection Time
User’s Manual U13952EJ3V1UD
1/f
1/f
1/f
1/f
X
X
X
X
410 s
1.64 ms
6.55 ms
26.2 ms
Operation at f
X
= 5.0 MHz