UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 254

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

address at 0000H and 0001H by RESET input.
item is set to the status shown in Table 17-1. Each pin is high impedance during reset input or during the oscillation
stabilization time just after reset release.
oscillation stabilization time (2
released after reset, and program execution is started after the oscillation stabilization time (2
Figures 17-2 through 17-4).
252
The following two operations are available to generate reset signals.
(1) External reset input via RESET pin
(2) Internal reset by program loop time detected by the watchdog timer
The external and internal resets have no functional differences. In both cases, program execution starts at the
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware
When a high level is input to the RESET pin, the reset is released and program execution is started after the
Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin.
Count clock
RESET
2. When the STOP mode is released by reset, the STOP mode contents are held during reset
input. However, the port pins become high impedance.
15
/fx) has elapsed. The reset applied by the watchdog timer overflow is automatically
Figure 17-1. Block Diagram of Reset Function
CHAPTER 17 RESET FUNCTION
User’s Manual U13952EJ3V1UD
Watchdog timer
Reset controller
Stop
Over-
flow
Reset signal
Interrupt function
15
/fx) has elapsed (see