UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 209

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

LCDC0
(3)
Note Specify an LCD source clock (f
Remarks 1. f
Symbol
LCD clock control register 0 (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock.
The frame frequency is determined according to the LCD clock and the number of time slices.
LCDC0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets LCDC0 to 00H.
For example, Table 14-3 lists the frame frequencies used when f
source clock (f
Number of Time Slices
Static
2
3
4
LCDC03
LCDC01
0
0
1
1
0
0
1
1
7
0
2. f
3. The parenthesized values apply to operation at f
LCDC02
LCDC00
X
XT
: Main system clock oscillation frequency
: Subsystem clock oscillation frequency
0
6
0
1
0
1
0
1
0
1
LCD Clock (LCDCL)
LCD
f
f
f
f
f
f
f
f
X
XT
X
X
LCD
LCD
LCD
LCD
).
0
5
/2
/2
/2
(32.768 kHz)
7
5
3
/2
/2
/2
/2
Frequency
(39.1 kHz)
(156.3 kHz)
(625 kHz)
Figure 14-4. Format of LCD Clock Control Register 0
6
7
8
9
0
4
LCDC03 LCDC02 LCDC01 LCDC00
CHAPTER 14 LCD CONTROLLER/DRIVER
3
Table 14-3. Frame Frequencies (Hz)
LCD
) frequency of at least 32 kHz.
(64 Hz)
User’s Manual U13952EJ3V1UD
f
2
XT
Selection of LCD source clock frequency (f
64
32
21
16
/2
9
Selection of LCD clock (LCDCL) frequency
1
0
(128 Hz)
f
128
XT
64
43
32
X
/2
= 5.0 MHz or f
Address
8
FFB2H
XT
After reset
(256 Hz)
(32.768 kHz) is supplied to the LCD
00H
f
XT
XT
256
128
85
64
/2
= 32.768 kHz.
LCD
7
)
Note
R/W
R/W
(512 Hz)
f
XT
512
256
171
128
/2
6
207