UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 95

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Symbol
(3)
Note Bit 5 is read only.
Caution Bits 0, 1, 2, 3, 6, and 7 must be fixed to 0.
CSS
Subclock control register (CSS)
CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies how
the CPU clock operates.
CSS is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSS to 00H.
CSS0
CLS
7
0
0
1
0
1
Operation based on the output of the divided main system clock
Operation based on the subsystem clock
Divided output from the main system clock oscillator
Output from the subsystem clock oscillator
6
0
CLS CSS0
5
Figure 5-4. Format of Subclock Control Register
4
3
0
Selection of main system or subsystem clock oscillator
CHAPTER 5 CLOCK GENERATOR
User’s Manual U13952EJ3V1UD
2
0
1
0
CPU clock operation status
0
0
Address
FFF2H
After reset
00H
R/W
R/W
Note
93