UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 276

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

274
CALL
CALLT
RET
RETI
PUSH
POP
MOVW
BR
BC
BNC
BZ
BNZ
BT
BF
DBNZ
NOP
EI
DI
HALT
STOP
Mnemonic
Remark
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
!addr16
[addr5]
PSW
rp
PSW
rp
SP, AX
AX, SP
!addr16
$addr16
AX
$saddr16
$saddr16
$saddr16
$saddr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
C, $addr16
saddr, $addr16
Operands
CHAPTER 20 INSTRUCTION SET
Bytes
User’s Manual U13952EJ3V1UD
3
1
1
1
1
1
1
1
2
2
3
2
1
2
2
2
2
4
4
3
4
4
4
3
4
2
2
3
1
3
3
1
1
Clocks
10
10
10
10
10
10
6
8
6
8
2
4
4
6
8
6
6
6
6
6
6
6
6
8
8
6
6
8
2
6
6
2
2
(SP
PC
(SP
PC
PC
PC
PC
PSW
(SP
(SP
PSW
rp
SP
AX
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
B
C
(saddr)
PC
No Operation
IE
IE
Set HALT mode
Set STOP mode
H
H
L
H
H
H
B 1, then PC
C 1, then PC
1 (Enable interrupt)
0 (Disable interrupt)
1)
1)
1)
1)
(SP + 1), rp
AX
SP
addr16, SP
addr16
PC + 2 + jdisp8
PC + 2 + jdisp8 if CY = 1
PC + 2 + jdisp8 if CY = 0
PC + 2 + jdisp8 if Z = 1
PC + 2 + jdisp8 if Z = 0
PC + 4 + jdisp8 if (saddr.bit) = 1
PC + 4 + jdisp8 if sfr.bit = 1
PC + 3 + jdisp8 if A.bit = 1
PC + 4 + jdisp8 if PSW.bit = 1
PC + 4 + jdisp8 if (saddr.bit) = 0
PC + 4 + jdisp8 if sfr.bit = 0
PC + 3 + jdisp8 if A.bit = 0
PC + 4 + jdisp8 if PSW.bit = 0
PC + 3 + jdisp8 if (saddr)
(00000000, addr5), SP
(00000000, addr5 + 1),
(SP + 1), PC
(SP + 1), PC
A, PC
(SP + 2), SP
(SP), SP
CPU
(saddr)
(PC + 3)
(PC + 1)
PSW, SP
rp
L
) selected by the processor clock control
H
, (SP
X
L
Operation
H
H
1, then
L
L
SP + 1
, (SP
, (SP
SP
PC + 2 + jdisp8 if B
PC + 2 + jdisp8 if C
2)
(SP), SP
(SP),
(SP), SP
SP
SP + 3, NMIS
2
rp
2)
2)
L
1
, SP
SP
0
(PC + 3)
(PC + 1)
SP + 2
SP + 2
SP
2
0
L
L
,
,
0
2
0
Z AC CY
R R R
R R R
Flag