UPD78F9418AGK-9EU Renesas Electronics America, UPD78F9418AGK-9EU Datasheet - Page 107

• Manufacturer Part Number: UPD78F9418AGK-9EU
• Manufacturer: Renesas Electronics America

Specifications of UPD78F9418AGK-9EU

• Lead Free Status / Rohs Status: Supplier Unconfirmed

TMC50
Symbol
Notes 1. Bit 7 is read-only.
Remarks 1. f
2. If the count clock is set to f
3. When reading, specify the main system clock as the CPU clock (PCC1 = 0, CSS0 = 0 or PCC1 = 1,
CPT501
TCL501
TOC50
TOD50 TOF50 CPT501 CPT500 TOC50 TCL501 TCL500 TOE50
TOD50
TOF50
TOE50
Other than
above
0
1
7
0
1
0
0
1
1
0
1
0
0
0
1
reading, set the CPU clock to the main system clock high-speed mode (PCC1 = 0, CSS0 = 0) (see
Figure 5-2).
CSS0 = 0) (see Figure 5-2).
2. The parenthesized values apply to operation at f
CPT500
TCL500
X
<6>
Timer output is “0”
Timer output is “1”
Clear by reset and software
Set by overflow of 16-bit timer
Inverse disabled
Inverse enabled
Output disabled (port mode)
Output enabled
: Main system clock oscillation frequency
0
0
1
0
1
1
Capture operation disabled
Rising edge of CPT5
Falling edge of CPT5
Both edges of CPT5
f
f
Setting prohibited
X
X
Figure 6-2. Format of 16-Bit Timer Mode Control Register 50
5
/2
(5.0 MHz)
5
(156.3 kHz)
4
Note 2
3
Note 3
X
CHAPTER 6 16-BIT TIMER 50
(TCL501 = 0, TCL500 = 0), the capture function cannot be used. When
2
User’s Manual U13952EJ3V1UD
16-bit timer 50 count clock selection
Timer output data inverse control
16-bit timer 50 output control
1
Capture edge selection
Timer output data
Overflow flag set
<0>
X
Address
= 5.0 MHz.
FF48H
After reset
00H
R/W
R/W
Note 1
105