LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 119
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
8.5.21 I
Table 98.
The I2CPADCFG register allows configuration of the I
order to support various I
the 4 bits in I2CPADCFG should be 0, the default value for this register. For Fast Mode
Plus, the SDADRV0 and SCLDRV0 bits should be 1. For non-I
be desirable to turn off I
to 1. See
Table 99.
PINMODE
_OD4
28
29
31:30
I2CPADCFG Symbol
0
1
2
3
31:4
2
C Pin Configuration register (I2CPADCFG - 0x4002 C07C)
Table 99
Open Drain Pin Mode select register 4 (PINMODE_OD4 - address 0x4002 C078) bit
description
I
description
2
Symbol
P4.28OD
P4.28OD
-
C Pin Configuration register (I2CPADCFG - address 0x4002 C07C) bit
SDADRV0
SDAI2C0
SCLDRV0
SCLI2C0
-
All information provided in this document is subject to legal disclaimers.
below.
Rev. 2 — 19 August 2010
2
Value Description
0
1
C filtering and slew rate control by setting SDAI2C0 and SCLI2C0
2
C-bus operating modes. For use in standard or Fast Mode I
Value Description
0
1
0
1
0
1
0
1
Port 4 pin 28 open drain mode control.
P4.28 pin is in the normal (not open drain) mode.
P4.28 pin is in the open drain mode.
Port 4 pin 29 open drain mode control, see P4.28OD
Reserved.
Drive mode control for the SDA0 pin, P0.27.
The SDA0 pin is in the standard drive mode.
The SDA0 pin is in Fast Mode Plus drive mode.
I
The SDA0 pin has
control enabled.
The SDA0 pin has
control disabled.
Drive mode control for the SCL0 pin, P0.28.
The SCL0 pin is in the standard drive mode.
The SCL0 pin is in Fast Mode Plus drive mode.
I
The SCL0 pin has
control enabled.
The SCL0 pin has
control disabled.
Reserved.
2
2
C
C
mode control for the SDA0 pin, P0.27.
mode control for the SCL0 pin, P0.28.
Chapter 8: LPC17xx Pin connect block
I
I
I
I
2
2
2
2
C
C
C
C
2
glitch filtering and slew rate
glitch filtering and slew rate
glitch filtering and slew rate
glitch filtering and slew rate
C pins for the I2C0 interface only, in
2
C use of these pins, it may
UM10360
© NXP B.V. 2010. All rights reserved.
119 of 840
Reset
value
0
0
NA
Reset
value
0
0
0
0
NA
2
C,
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