LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 319
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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15.3 Pin description
Table 288: UART1 Pin Description
UM10360
User manual
Pin
RXD1 Input
TXD1 Output Serial Output. Serial transmit data.
CTS1 Input
DCD1 Input
DSR1 Input
DTR1 Output Data Terminal Ready. Active low signal indicates that the UART1 is ready to establish connection with
RI1
RTS1 Output Request To Send. Active low signal indicates that the UART1 would like to transmit data to the external
Type
Input
Description
Serial Input. Serial receive data.
Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted data via
TXD1 from the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement value
of this signal is stored in U1MSR[4]. State change information is stored in U1MSR[0] and is a source for a
priority level 4 interrupt, if enabled (U1IER[3] = 1).
Clear to send. CTS1 is an asynchronous, active low modem status signal. Its condition can be checked by
reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the Modem Status Register (MSR)
indicates that CTS1 has changed states since the last read from the MSR. If the modem status interrupt is
enabled when CTS1 changes levels and the auto-cts mode is not enabled, an interrupt is generated. CTS1
is also used in the auto-cts mode to control the transmitter.
Data Carrier Detect. Active low signal indicates if the external modem has established a communication
link with the UART1 and data may be exchanged. In normal operation of the modem interface
(U1MCR[4]=0), the complement value of this signal is stored in U1MSR[7]. State change information is
stored in U1MSR3 and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).
Data Set Ready. Active low signal indicates if the external modem is ready to establish a communications
link with the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of
this signal is stored in U1MSR[5]. State change information is stored in U1MSR[1] and is a source for a
priority level 4 interrupt, if enabled (U1IER[3] = 1).
external modem. The complement value of this signal is stored in U1MCR[0].
The DTR pin can also be used as an RS-485/EIA-485 output enable signal.
Ring Indicator. Active low signal indicates that a telephone ringing signal has been detected by the
modem. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this signal is
stored in U1MSR[6]. State change information is stored in U1MSR[2] and is a source for a priority level 4
interrupt, if enabled (U1IER[3] = 1).
modem. The complement value of this signal is stored in U1MCR[1].
In auto-rts mode, RTS1 is used to control the transmitter FIFO threshold logic.
Request to send. RTS1 is an active low signal informing the modem or data set that the UART is ready to
receive data. RTS1 is set to the active (low) level by setting the RTS modem control register bit and is set to
the inactive (high) level either as a result of a system reset or during loop-back mode operations or by
clearing bit 1 (RTS) of the MCR. In the auto-rts mode, RTS1 is controlled by the transmitter FIFO threshold
logic.
The RTS pin can also be used as an RS-485/EIA-485 output enable signal.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 15: LPC17xx UART1
UM10360
© NXP B.V. 2010. All rights reserved.
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