LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 320

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
15.4 Register description
Table 289: UART1 register map
[1]
UM10360
User manual
Name
U1RBR
(when DLAB =0)
U1THR
(when DLAB =0)
U1DLL
(when DLAB =1)
U1DLM
(when DLAB =1)
U1IER
(when DLAB =0)
U1IIR
U1FCR
U1LCR
U1MCR
U1LSR
U1MSR
U1SCR
U1ACR
U1FDR
U1TER
U1RS485CTRL
U1ADRMATCH
U1RS485DLY
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Description
Receiver Buffer Register. Contains the next received character to
be read.
Transmit Holding Register. The next character to be transmitted is
written here.
Divisor Latch LSB. Least significant byte of the baud rate divisor
value. The full divisor is used to generate a baud rate from the
fractional rate divider.
Divisor Latch MSB. Most significant byte of the baud rate divisor
value. The full divisor is used to generate a baud rate from the
fractional rate divider.
Interrupt Enable Register. Contains individual interrupt enable bits
for the 7 potential UART1 interrupts.
Interrupt ID Register. Identifies which interrupt(s) are pending.
FIFO Control Register. Controls UART1 FIFO usage and modes.
Line Control Register. Contains controls for frame formatting and
break generation.
Modem Control Register. Contains controls for flow control
handshaking and loopback mode.
Line Status Register. Contains flags for transmit and receive status,
including line errors.
Modem Status Register. Contains handshake signal status flags.
Scratch Pad Register. 8-bit temporary storage for software.
Auto-baud Control Register. Contains controls for the auto-baud
feature.
Fractional Divider Register. Generates a clock input for the baud
rate divider.
Transmit Enable Register. Turns off UART transmitter for use with
software flow control.
RS-485/EIA-485 Control. Contains controls to configure various
aspects of RS-485/EIA-485 modes.
RS-485/EIA-485 address match. Contains the address match value
for RS-485/EIA-485 mode.
RS-485/EIA-485 direction control delay.
UART1 contains registers organized as shown in
(DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table
289. The Divisor Latch Access Bit
RO
WO
RO
R/W
R/W
Access Reset
RO
WO
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
Chapter 15: LPC17xx UART1
Value
NA
NA
0x01
0x00
0x00
0x01
0x00
0x00
0x00
0x60
0x00
0x00
0x00
0x10
0x80
0x00
0x00
0x00
UM10360
[1]
© NXP B.V. 2010. All rights reserved.
0x4001 0008
0x4001 0008
0x4001 0018
0x4001 001C
0x4001 0054
Address
0x4001 0000
(when DLAB=0)
0x4001 0000
(when DLAB=0)
0x4001 0000
(when DLAB=1)
0x4001 0004
(when DLAB=1)
0x4001 0004
(when DLAB=0)
0x4001 000C
0x4001 0010
0x4001 0014
0x4001 0020
0x4001 0028
0x4001 0030
0x4001 004C
0x4001 0050
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