LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 312

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 283: UARTn IrDA Control Register (U0ICR - 0x4000 C024, U2ICR - 0x4009 8024, U3ICR - 0x4009 C024) bit
Table 285: UARTn Fractional Divider Register (U0FDR - address 0x4000 C028, U2FDR - 0x4009 8028, U3FDR -
UM10360
User manual
Bit
2
5:3
31:6
Bit
3:0
7:4
31:8 -
Function
DIVADDVAL
MULVAL
Symbol
FixPulseEn
PulseDiv
-
description
0x4009 C028) bit description
14.4.12 UARTn Fractional Divider Register (U0FDR - 0x4000 C028, U2FDR -
Value
0
1
NA
Value Description
NA
The PulseDiv bits in UnICR are used to select the pulse width when the fixed pulse width
mode is used in IrDA mode (IrDAEn = 1 and FixPulseEn = 1). The value of these bits
should be set so that the resulting pulse width is at least 1.63 µs.
possible pulse widths.
Table 284: IrDA Pulse Width
0x4009 8028, U3FDR - 0x4009 C028)
The UART0/2/3 Fractional Divider Register (U0/2/3FDR) controls the clock pre-scaler for
the baud rate generation and can be read and written at the user’s discretion. This
pre-scaler takes the APB clock and generates an output clock according to the specified
fractional requirements.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be greater than 2.
FixPulseEn
0
1
1
1
1
1
1
1
1
When 1, enabled IrDA fixed pulse width mode.
Configures the pulse when FixPulseEn = 1. See text below for details.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Description
Baud-rate generation pre-scaler divisor value. If this field is 0, fractional
baud-rate generator will not impact the UARTn baudrate.
Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for
UARTn to operate properly, regardless of whether the fractional baud-rate
generator is used or not.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
PulseDiv
x
0
1
2
3
4
5
6
7
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
IrDA Transmitter Pulse width (µs)
3 / (16 × baud rate)
2 × T
4 × T
8 × T
16 × T
32 × T
64 × T
128 × T
256 × T
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
Chapter 14: LPC17xx UART0/2/3
Table 284
UM10360
© NXP B.V. 2010. All rights reserved.
shows the
0
0
Reset value
0
1
0
Reset value
0
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